Altium filled vias
Altium filled vias. The vias are filled with non-conductive epoxy and cured. Click the Fill button () in the drop-down on the Active Bar located at the top of the workspace. There are a number of processes needed to fabricate a bare PCB and each one takes money and time. The purpose of tenting is to limit the number of exposed conductive pads on the PCB. Process: Application of mask over Type V. If you don’t see a discussed feature in your software, contact Altium Sales to find out more. In the next part, we will examine proper placement of vias, and special use cases such Feb 23, 2018 · In the bottom right-hand corner select the PCB menu. Dec 9, 2022 · Stitching vias are something you often see spread around the surface layer of a PCB. Larger aspect ratios of 1:1, or even as high as 2:1, can be fabricated, but they bring reliability concerns. I have seen designs using this method. When a high-speed signal travels between PCB layers through a copper barrel, it can be distorted. Once your design is ready for a thorough design review and manufacturing, your team can share and collaborate in real time through the Altium 365™ platform. This can be attributed to the thermal conductivity differences for the air-exposed trace and the via current-carrying capacity. Through-hole Via: The through-hole via is the most common type of via in PCB design. In the following, you will find a comparison of the technical Sep 1, 2021 · Level B Minimum Hole Size = maximum lead diameter + 0. Option 2 is useful because it allows you to embed any component in your libraries without modifying footprints. Concerning the clearance (of component), it is 0,254 mm. The unused part of the metallization hole is drilled at a larger diameter to a certain depth. The barrel-shaped body of the via is formed when the board is Dec 11, 2021 · Vias shall be filled with non-conductive epoxy. The last used menu button will become the Mar 22, 2021 · Understanding Coplanar Waveguide with Ground. 5mm sizes, filling results may vary depending on the surface tension. By incorporating staggered and stacked vias in your design, you can get a compact, efficacious circuit board. Laser drilled 0. Vias are three-dimensional objects and have a barrel-shaped body in the Z-plane (vertical) with a flat ring on each (horizontal) copper layer. It is pain in the ass having all the vias in the schematic part of the project. Resulting protrusion not to exceed XXXX mils per IPC-6012 Class 3 requirements. Benefits of using blind/buried vias include: More routing Benefits of Copper Filled Vias. In effect, they compensate for insufficient interplane capacitance and reduce PDN impedance such that any ringing in the PDN voltage is minimized. Apr 5, 2022 · There are three primary types of vias: Through: spans the entire stack of the board. Mar 22, 2021 · Applying a thermal relief pad to a specific SMD pad or through-hole pin based in the pad/pin properties. Nov 26, 2018 · A via is a primitive design object. The greater the annular ring, the greater the copper connection around the drill hole will be. The hole can be partially filled with an LPI solder mask or the filling can be washed off. Improvements in fabrication techniques and the introduction of laser drilling gave the ability to create very small (<10 mil) vias, formed from a surface layer to the next signal layer down. Jan 15, 2016 · Under it, I put two Fills (one on top and one on bottom layer). Buried Vias — inner layers only, does not connect to either outer surface. Tenting a via has both positive and negative impacts on the PCB. For work, we use Altium, but there is no way to specify this, so we include it in our fab notes. Jul 26, 2017 · In the PCB Library Editor - to place an arc: Choose the required standard arc mode from the Place menu. com IPC - Vias 10 Filled and Covered Via (Type VI Via) A Type V via with a secondary covering of material (liquid or dry film soldermask) applied over the via. 25 mm (3) Determine the pad sizes based on IPC-2221. 1 mm trace in a Dec 3, 2021 · Design Basics and the HDI PCB Manufacturing Process. This time we will examine aspects of via placement, problems with via placement leading to plane voiding, and finally looking at some unique use cases of vias termed transfer vias and stitching vias. Blind: starts on a surface layer and ends in an internal layer. Typically this differential routing will interface to an external differential transmission system, such as a connector and cable. For the latest, read: PCB Editor - Interactive Routing for version 21. In cases where the pin pitch is too narrow for a traditional escape Oct 27, 2021 · The property settings for each type of object are defined in two different ways: Pre-placement settings – most Via object properties, or those that can logically be pre-defined, are available as editable default settings on the PCB Editor – Defaults page of the Preferences dialog (accessed from the button at the top-right of the design space). Mar 29, 2024 · Vias with soldermask can be printed over with silkscreen; those without soldermask should have the same surface finish (HASL / ENIG) as other exposed copper. Apr 26, 2019 · Tenting a via means you create a tent-like shape over the hole to cover the via. 2 mm pitch traces with 0. In this case the Peters overwhelming demand, has lead been due available to a better for CTE a longer match time with but standard PCB Aug 12, 2022 · In response to some of our previous videos, Tech Consultant Zach Peterson has been asked about when designers should do vias in pads - specifically surroundi Aug 6, 2019 · You can also place filled and capped vias directly under the thermal solder pad for circuit board applications that have a thickness greater than 0. There are two types of lasers used in this process: May 23, 2017 · Low aspect ratio: Contrary to through-hole vias in typical PCBs, microvias have small aspect ratio. Mar 22, 2021 · A thermal via does not have a particularly special structure; these vias are typically through-hole vias that can be filled with conductive epoxy and plated over. Register Now. Staggered and stacked vias are well adapted nowadays. PCBs designed using high-density interconnect (HDI) techniques tend to be smaller as more components are packed in a smaller space. Altium version: 1,0,11 (build 97) Altium NEXUS. May 25, 2018 · All high-density PCBs rely on specific via styles to make connections into the inner layers without taking up space for routing. The covering material may be applied from either one side (Type VI-a) or both sides (Type VI-b) of the via structure. com/altium-designer-19-how-to- www. It is a hole that extends through the entire thickness of the board and connects all the layers. Polygon pours are used to create a solid or hatched (lattice) area on a PCB layer, using either Region objects or a combination of Track and Arc objects. Essentially a via is a small drilled hole that goes through two or more adjacent layers; the hole is plated with metal (often copper) that forms an electrical connection through the insulating Mar 19, 2020 · What is the minimum size of VIA and VIA-in-PAD which I can use in my board? What kind of VIA in PAD I should choose? How much is it going to cost? Everything The following are some of the most common types of vias in PCB design: 1. Nov 3, 2023 · A via is a primitive design object. Jun 17, 2019 · In Altium, a newly placed via is assigned to not connected to any net. Also referred to as copper pours, polygon pours are similar to a region except that they can fill Apr 12, 2022 · After the layers are pressed together into a single multi-layer board, thru-hole vias are drilled (via number 3). You can assign a net to each of these layers or share a power plane between a number of nets by splitting it into two or more isolated areas. If you use the design rules, you will always have the option to manually apply Dec 13, 2017 · Click the button on the Wiring toolbar. Dec 9, 2021 · When you need to select and assign tented vias in your PCB layout, use the complete set of easy-to-use CAD tools in Altium Designer ®. . Another type of multi-layer board fabrication technology is called Build-up technology, where layers are added one after the other, often over a Aug 10, 2018 · In Altium Designer, you can create your planes either as a negative (Internal) plane or as a positive plane (Polygon Pour). Another type of multi-layer board fabrication technology is called Build-up technology, where layers are added one after the other, often over a Feb 11, 2019 · ELIC PCBs that require HDI design can use buried vias to connect between individual layers, rather than selectively spanning pairs of layers. Oct 26, 2021 · The use of copper pour and via stitching is sometimes framed as an always-never type of decision, and with a variety of explanations to justify its use or omission. 20 mm (2) Level C Minimum Hole Size = maximum lead diameter + 0. The filled copper plating should continue around the edge of the via hole and extend onto the annular ring surrounding the via pad. In compliance with the IPC-A-600 and IPC-6012 class 2, holes that require Via Filling must have a minimum of 60% of the hole volume filled. Copper-Epoxy-Filled & Capped Vias. All vias in the stack must be filled with copper in order to create the required electrical contacts A via is a primitive design object. Apr 23, 2019 · Now reading version 19. This pad is intended to transfer heat to vias and then to the ground plane. 3mm to 0. IsBuriedVia: All vias that start on an internal layer and end on another internal layer, that are Apr 28, 2020 · Here, we can see that thin traces tend to run hotter than the via connected to them, with a temperature difference of only a few °C. Plugged vias are fully filled. The PCB trace width and the spacing to the grounded copper regions need to be designed to set the designed impedance to the desired value. #viaundesmdpad0:00 Introduction about Via under SMD Pad Design rule. Bittele only performs Via Tenting upon client request. All of the various types of vias that can be fabricated can be defined in the Via Types tab of the Layer Stack Manager. (4 - 6) from the IPC-2221 Standardshould be used to determine pad diameter. I also checked the option "Allow vias under SMD pads" in design rules. Vias are used to form a vertical electrical connection between two or more electrical layers of a PCB. @MCG The image shows they've already assigned the correct net to the via. Summit focuses on complex rigid and rigid-flex products and offers extensive expertise in RF/Microwave applications. IsBlindVia: All vias that start on a surface layer and end on an internal layer, that are not a µVia. Buried microvias: These microvias are basically blind vias that are confined to internal layers. You have to buy IPC standards. An HDI PCB uses blind, buried, and micro vias, vias in Figure 1 - Dupont CB100 Conductive Via Fill. Important parameters are resin content, aspect ratio of the hole and the thickness of the core involved. To define a new Via Type, switch to the Via Types tab of the Layer Stack Manager. In this second “Vias 101” article, we will be continuing on from our previous discussion of essential via parameters. a. Mar 22, 2021 · Customize Your PCB Drill Sizes With Altium Designer Every PCB will need some holes, vias, slots, and other features that are defined in a PCB layout. In this case the GND should be minimum 0,5mm for the hole and 1 mm for diameter. In this first “Vias 101” article, we will be covering the very basics of vias in PCB design, including their characteristic parameters, which standard vias should be used in designs, and talk briefly about current handling capabilities. These types of via covering are possible: Simply Covering: Via Tenting or Tented Vias. The PCB tab opens and by default docks to the left-hand side. With Altium Designer’s comprehensive stackup and thermal via features, you can easily create your layer stack, thermal vias, and layout in a single program. And multiple small vias can provide a lower resistance path than one big one (which is mostly air in the middle rather than copper). taken from here. After determining minimum hole size, Eqs. If the signal layer usage results in a stub being present, and Apr 12, 2022 · All of these Via Types are supported in Altium Designer. Jul 2, 2020 · Via-in-pad design is the practice of putting a via into the metal pad of a surface-mount component footprint. It is used to form a vertical electrical connection between two or more electrical layers of a PCB. In this way, a thermal via will function as a heat pipe, aiding heat transfer away from a component on one of the surface layers and into the interior layers. When you need to design your PCB vias and routing to ensure you comply with IPC-6012 Class 3 annular ring standards, use the padstack design and routing features in Altium Designer ®. With a mask plugged via, (a. 1. These are referred to as µVias. Like a Fill, a Region does not avoid other objects, such as pads, vias, tracks, fills, other regions or text. 3mm have the best chance of getting filled, while between 0. A laser is used to ablate the copper on the outer layer as well as the insulating material between layers 1 and 2. Like many aspects of a physical PCB layout, via stitching and copper pour can be like acid: quite useful if implemented properly, but also dangerous if used indiscriminately. If someone is using copper pour correctly, then they will ideally calculate an appropriate stitching via separation distance such that the via array suppresses crosstalk/interference. Vias in the pads are useful in high speed designs since they reduce trace length and therefore inductance (i. The new Pad Via Template library is given a default name of PvLib1. Oct 20, 2022 · Vias 101 Part 1. In the example below, the designer has to exclude the unused part from 6 to 4 layers (Fig. In most other professional PCB design tools Apr 19, 2024 · The PCB editor supports up to 16 internal power planes. The drawing objects are accessed via the button shown below, click and hold anywhere on that button to access all drawing objects. PCB Library Editor - the following methods of access are available: Choose Place » Fill from the main menus. Vias require an understanding of annular rings to work properly, though. Design teams can use Altium 365 to share Dec 13, 2019 · ale210 , 01-28-2020, 08:01 AM. Filling a via with epoxy and capping it with copper prevents the solder flow from any uncontrolled solder flow. Fill material ONLY through hole vias can be filled, so Blind Via Holes can NOT be filled. Power planes are created in the negative. With altium, I added a via stitching on these fills. Thanks for your answer, i have two rules for the via (power and all). The barrel-shaped body of the via is formed when the board is Jun 8, 2022 · 9:00 am to 4:00 pm PT. Via filling example (blue is the copper fill, there is no solder mask (green) on this via so it is easier to be filled by you, the user/engineer): Taken from here Mar 29, 2024 · A region ( Place » Solid Region) is a design object that is used for defining polygonal shapes. In this case the Peters overwhelming demand, has lead been due available to a better for CTE a longer match time with but standard PCB Feb 1, 2023 · This allows blind and buried vias to connect between the surfaces of these boards. 0. In applications involving high heat, keeping the heat away from the board will increase its lifespan and prevent defects. k. Completely Filled: Via Filling or Filled Vias. See more How To Videos at: https://resources. Drill vias and coat the via barrels with a metallization layer to ensure conduction through the core. A common application for this is on a BGA design where vias are commonly found in very close proximity to the BGA's SMD pads. Feb 13, 2018 · Enter vias; our ingenious solution to vertically connecting each layer. (Click and hold an Active Bar button to access other related commands. A Rectangle is a non-filled set of connected tracks or lines limited to a rectangle shape (with corner options) which can be drawn on any layer. The main drawback of via filling is the increased complexity and cost of the manufacturing process, as it requires precise filling and plating steps. May 4, 2023 · 6. Vias shall be plated over. Figure 1 - Dupont CB100 Conductive Via Fill. You see this the most on QFN's and other packages that have a ground pad on the bottom of the part in the center. The following images show Pads in Draft Mode to enable visibility of Solder Mask underneath a Pad. 2mm, 0. Jan 11, 2018 · Controlled Depth Drilling (CDD), also known as back drilling, is a technique used to remove the unused portion, or stub, of copper barrel from a thru-hole in a printed circuit board. Defining a Via Type. Buried: starts and ends in an internal layer. May 12, 2022 · Many users of Altium Designer come from using other CAD tools like Cadence Allegro, OrCAD, P-CAD, or Mentor PADS. Non-Conductive: product produ the The non -conductive products are similarly popularized by two taken cts —Peters PP2795 epoxy and San-Ei Kagaku PHP-900 epoxy. Mask Filled or Non-Conductive Filled via), specific measures are taken to ensure the via is plugged and sealed with mask and the annular ring is covered. 008 in (0. Click the Fill button () in the drop-down on the Active Bar located at the top of the design space. The PCB Editor - Interactive Routing page of the Preferences dialog. As far as spec'ing them, I use the method described by evb149: Dec 20, 2018 · The filled via will prevent solder from wicking through the via hole and onto the bottom of the board when mounting through-hole components. Oct 16, 2019 · Laser Drilled Blind Vias: These are created after all of the layers in a PCB have been laminated and before the outer layer has been etched and plated. In today’s episode, Gerry will help us untangle IPC 4761 and get Aug 7, 2019 · More landless vias including three more examples of ‘invisible vias’. 3:00 Information about design rule for V It is very important to note that the smaller the via hole size, the better the result will be. It should be noted that, while via tenting does often close up smaller May 27, 2019 · The more advanced via styles can be combinations of these, as we will see below. When a via is tented, the manufacturer used a solder mask to enclose the opening. However, Option 1 is also useful because it shows a more realistic view of the cavity cutout in 3D. So if the pad is 100 x 100, then the expansion would be -50. Apr 13, 2020 · If a via is meant to carry current why not go for a solid copper filled via than a plated via (which is hollow/nonconductive at the center)? Because a plated via hole is "good enough". 4mm or 0. The other option is usage as multiple parallel connections between layers Oct 6, 2021 · Click the button on the Wiring toolbar. It seems a pretty big oversight, but there it is… FWIW, a filled and plated/copper capped via is an IPC Type VII via. 3). The aspect ratio of these vias is preferably 0. Fine pitch BGA Aug 28, 2018 · The IPC 6012E standards recently added a copper wrap plating requirement to via-in-pad structures. Peel strength is much lower when you epoxy-fill is in the center and plated over. 1mm blind via in a 0. This is then exposed to UV Nov 16, 2023 · A new pad/via template library can be created by the following ways: Select File » New » Library command from the main menus and select the Pad Via Library option from the File region of the New Library dialog that opens, then click Create . This is always driven by the components used in the PCB, namely fine-pitch BGAs with many high pin counts. Blind and buried vias can be placed into arrangements: Stacked blind and buried vias; Offset or staggered Vias; Boomerang vias; Staggered vias use a small trace to connect them on the internal layer, and they are more reliable than stacked blind and buried vias. These features need to be reflected in fabrication documents, and designers need tools to help them automate this process of creating documentation directly from their designs. Through-hole vias are typically used for high-current connections or for providing Oct 19, 2023 · Via filling can be particularly useful in high-density designs, where the filled vias can act as thermal vias, helping to dissipate heat from high-power components. In addition, filled and capped vias ensure excellent soldering. Pros. There are many advantages to using VIP design, and here are a few of them: VIPs help with the escape routing of large parts that have fine pitch pins, such as BGAs. Summit is an advanced technology manufacturer creating custom printed circuit boards. SMD components and vias on a green PCB. Jun 13, 2019 · Drill & Metalize Blind/Buried Vias - this step is only required if the board is to feature blind and/or buried vias. Via Tenting. The best manufacturers can likely produce any via you need. For total removal; the Negative value must be 1/2 the size of the pad. 35mm lands on the vias; d. A common application for this is on a BGA design where vias are commonly found in very close proximity to the BGA’s SMD pads. The barrel-shaped body of the via is formed when the board is Oct 20, 2022 · Vias 101 Part 2. Through-hole vias should be tented on both sides to reduce the chances of any chemical entrapment. Partially Filled: Via Plugging or Plugged Vias. IPC-4761 Via Types The document describes the possibilities of supporting several types of adapter protection according to the standardized IPC-4761 via types in Altium Designer with the advantages and disadvantages of each. Open the dropdown menu. Apr 15, 2020 · A region ( Place » Solid Region) is a design object that is used for defining polygonal shapes. two landless vias on a 0. May 24, 2023 · Place the footprint on an internal layer in the PCB layout, and then draw the cavity manually. PvLib. The three types of vias that can be created: blind (1), buried (2) and thru-hole. Sep 2, 2012 · 54. These rings are defined as the minimum distance between the drilled hole and the edge of the via trace. Their unique design enhances the density, as well as boosts the signal integrity and routing flexibility. Apr 5, 2020 · When placed between the power and ground planes, a decoupling capacitor is in parallel with the planes, which increases the total PDN capacitance. A Fill or Solid Region is a solid region similar to a polygon pour except it does not have options for fill style (like hatched), pour sequence, or connection style to vias and pads. First, we will look at the process of creating a negative or “Internal” plane within our Altium plane layers. 70 millimeters. 1:45 Defining Design rule for Via under SMD Pad. Unused Pad Shape Removal - removed unused pad and via copper Mar 12, 2006 · The internal of a via: As you can see current flows on the walls of the via. The design rule system and query system in Altium Designer allows you to mix and match these approaches for different types of components or groups of components. Jun 3, 2015 · This path is defined by placing PCB design objects – such as tracks, arcs and vias – on the copper layers, to create a continuous connection between the nodes. 1 mm trace; b. A Solid Region (commonly called Region) can be placed on any layer including signal (copper) layers. e. 1 mm landless vias and the proportional size if there were 0. 2mm) TH; c. Then we have vias that are. Sep 9, 2019 · A via is a primitive design object. Useful for component cavities. Select PCB from the menu. Print onto laminate the areas to etch; Etch Sep 9, 2019 · A via is a primitive design object. A via (Latin, 'path' or 'way') is an electrical connection between two or more metal layers, and are commonly used in printed circuit boards (PCB). Laminate/Expose/Develop Photoresist - apply a photo-resistive coating to the copper clad cores. Plugged: openings at surface layers are stuffed with liquid soldermask. A. The features available depend on your Altium product access level. Mar 22, 2021 · Complete Thermal Via Design and Layout in Altium Designer. The material for filling can be applied on a single side or both sides. Easier routing and fan-out of BGAs and other dense parts. Oct 22, 2020 · Altium Designer can help the engineer to improve the quality of high-speed signals in a rather simple way; one such method is called back drilling technology. Sep 25, 2018 · These structures may be filled with copper or left unfilled, although microvia-in-pad designs should use filled structures to provide a uniform placement for soldering. Via hole sizes less than 0. Browse our library of resources to learn more about pcb design and PCB vias. May 25, 2018 · The terms via-in-pad and VIPPO are sometimes used interchangeably. In an ELIC PCB, blind and buried vias can be stacked in order to access every layer in the board. Slight reduction in reliability when via is plated, epoxy-filled and plated over versus a via only plated in the final. Nov 16, 2023 · Differential pair routing is a design technique employed to create a balanced transmission system able to carry differential (equal and opposite) signals across a printed circuit board. IsThruVia: All vias that span from the top layer to the bottom layer. Tented: via surface covered with dry film soldermask. The barrel-shaped body of the via is formed when the board is Apr 3, 2018 · I have like 20 vias stitching area but with no via. One of the options for routing into inner layers as part of fanout routing is to use skip vias. Pad and via connections to power planes are controlled by the Plane design rules. Given the tolerance requirements on vias, you should check with your manufacturer regarding their Mar 27, 2019 · Watch to learn how you can setup and use microvias in your next PCB design. The burried vias will show up in the areas highlighted Aug 21, 2022 · Unfortunately, I don't think Altium allows specification of filled and plated vias, though they should given what the software costs. PCBs featuring copper-filled vias have the following advantages over boards that only have copper-plated vias: Thermal conductivity: Filling a via with copper increases its thermal conductivity. PCB Vias. If you fill the via with copper afterwards, it will be able to carry more current. The first thing to do when creating an internal plane is to add a design layer specifically for the plane. As the world of technology has evolved, so has the need to pack more capabilities into smaller packages. the connection goes straight from pad to plane rather than pad-trace-via-plane) You have to check whether your PCB house can do this though, and it may cost more (via will need to be plugged and plated over to provide a smooth Mar 19, 2019 · Why do we need to protect vias? Here to answer is Gerry Partida, Director of Engineering at Summit Interconnect Technologies. In effect, heat is dissipated from the via faster than it is dissipated from the Apr 12, 2022 · After the layers are pressed together into a single multi-layer board, thru-hole vias are drilled (via number 3). Coplanar waveguides are open quasi-TEM waveguide geometries that use copper pour and a ground plane to provide shielding along the length of a PCB trace. Select Hole Size Editor. 75:1. Find an entry that doesn't connect to either the Top Layer or Bottom Layer and select the check box. The epoxy used to plug the via can be either conductive or non-conductive. Because of this, they typically only span between a single layer. They also must obey the standard aspect ratio requirements to ensure reliability Sep 13, 2017 · Altium Designer includes a number of tools that can be used for the placement and removal of extra vias and pads, including: Via Stitching - place an array of vias across the entire board, or an area of the board. I plan to link them with vias in order to conduct better power and to user the bottom one for thermal dissipation. Workaround, You can create a PCB library/schematic via component and then use mechanical layer to represent filling. Mar 25, 2021 · So if it is needed to remove the Paste Mask from a Surface Mount Pad, a Negative expansion value is the only option. Read Article. Here's some of the advantages of no thermal reliefs: Greater heat transfer to the planes on the PCB. Altium Designer’s CAD tools are accessible alongside a complete set of simulation and production planning features. Via-in-pad design used for direct soldering should be filled with an epoxy to prevent wicking through the via hole, just as in VIPPO. Select the via, right click and select the net to attach to. Choose the required mode from the PCB Library Editor Active Bar. Via Shielding - place and array of vias along both edges of a route. Rather than placing these objects one by one to build up the connective path, you interactively route the connection. This requirement improves the reliability of the via plating and has the potential to reduce failures due to cracks Dec 20, 2017 · A polygon pour is a group design object that is made up of simpler primitive objects. Definition: Vias are filled with conductive copper, and then plated over with copper. There is generally no added cost or lead time requirement for this process, and it is normally used simply to prevent accidental contact between the annular rings of the vias and any other circuit elements. Originally posted by Frenky. Suitable for any type of untented via on one side or vias in pad Feb 3, 2024 · This helps isolate signals. Now consider bypass capacitors. Mar 18, 2019 · Place via in land to avoid delay and reduced real estate for routing. 5. The one view shows 0. FWIW, what you are asking for is an IPC Type VII via, as it is described in the IPC-4761 Standard. Here you define the Z-plane layer-spanning requirements of each of Mar 27, 2020 · Via Type Query Returns; IsVia: All via objects, regardless of the Via Type. Jun 18, 2021 · As discussed above, we use a specific via diameter for those vias, which is usually the smallest via we use on a PCB. Vias are a three-dimensional object, having a barrel-shaped body in the Z-plane (vertical) with a flat ring on each (horizontal) copper layer. In the PCB editor, interactive routing is an intelligent process. altium. Several technical or production-related demands for PCB manufacturing require via protection. eo mf cb pk gs ie bv xw wn bo